Instinct MI400 and Helios

I am writing this in the middle of October 2026, which makes this part like Part 29: a photograph of a machine still being unpacked. AMD previewed the MI400 family and its rack, Helios, in June 2025, showed a physical Helios rack in October 2025 and again on stage at CES in January 2026, and launched both on 23 July 2026, saying that Helios was in full production and that shipments would start in the third quarter. On 4 August Lisa Su told investors that the first shipments were on track for later that quarter. OpenAI has said it expects to bring Helios online from the fourth quarter of 2026, and Meta has said it is testing workloads on Helios racks before deploying them at scale. What I have not found, as of today, is a public report of a customer running Helios in production, or any independent measurement of an MI455X. AMD reports its third-quarter results on 3 November. So this part is written from AMD's specifications, the company's presentations at the Hot Chips conference in August, and the reporting around them, and every performance figure in it is AMD's own.

There was one public wobble on the way. In February 2026 the research firm SemiAnalysis reported that mass production had slipped and that customers would not see production volumes until 2027. An AMD executive replied on social media, in one word followed by "Right on target for H2 2026". The July launch and the August call bore AMD out on the dates it had given. How fast the volume follows is the open question.

The GPU

The MI455X is the GPU that goes in Helios, and its package follows the MI355X's plan with every number moved. Eight accelerator complex dies, now on TSMC's 2 nm-class N2 process, are bonded on top of two base dies that AMD calls fabric and cache dies, and each of those connects to an I/O die carrying the links to other GPUs, the CPU and the network; the base and I/O dies are on 3 nm. Around them sit twelve stacks of HBM4, each 36 GB on a 2,048-wire interface, for 432 GB at 23.3 TB/s. The whole assembly is held together on TSMC's CoWoS-L, a larger interposer built from bridges rather than one slab of silicon. AMD puts it at 320 billion transistors. It has not said how much power it draws; ServeTheHome, from the rack figures, estimates more than 2 kW.

Its peak arithmetic, by AMD's dense figures: 40 PFLOPS at four bits, 20 at six and eight bits, 5 at sixteen, from 256 work-group processors at up to 2.4 GHz. Multiply out and each work-group processor does about 65,000 four-bit operations per clock, four times a CDNA 4 compute unit. Against the MI355X of Part 28 that is four times the FP4 and FP8, one and a half times the memory, and nearly three times the bandwidth. The large cache in the base dies is now described as 192 MB of L2, shared by the whole chip, rather than as a separate Infinity Cache behind a smaller L2, and each half of it can deliver 27 TB/s.

A compute unit that works like a Radeon's

The most interesting change is not in the package. Part 10 described how AMD split its GPUs in 2020: RDNA for graphics, with 32-thread wavefronts and compute units in pairs, and CDNA for computing, which kept GCN's four SIMDs of 16 lanes, its 64-thread wavefronts and its four-cycle rhythm. CDNA 5 ends the split. AMD counts the MI455X in work-group processors, the RDNA unit, and its own specification lists them as wave32. Each one, according to the Hot Chips disclosures, has four SIMDs of 32 lanes that can issue two instructions at once, the dual issue of RDNA 3, and four scalar units, with 128 KB of vector registers per SIMD, 320 KB of local data share and a 64 KB L1 cache. Each compute die carries 34 of them and uses 32.

Why converge now? The case for wave64 in CDNA was the four-cycle rhythm that hid the pipeline and kept old supercomputer code running well. But in an AI chip most of the arithmetic happens in the matrix units, which do not care how the wavefront is cut, and what matters around them is moving data into place quickly, where a smaller, nimbler wavefront helps. And there is the software. AMD said in 2024 that it would merge its graphics and compute architectures into one, so that the same compiler, libraries and tuning would serve a Radeon on a desk and an Instinct in a data centre, the way CUDA has always served every Nvidia GPU. The MI455X is the data-centre half of that merger arriving first.

Two other additions echo things Nvidia did earlier. A tensor data mover copies blocks of a matrix from memory into the local data share in the background while the lanes compute, which is the job of the tensor memory accelerator Hopper introduced in Part 24. And the four-bit formats gained a finer scale option, one scale for every 16 numbers as well as every 32, which is the block size of Nvidia's NVFP4 from Part 27.

The science chip, split off

The MI455X does very little 64-bit arithmetic, about 5 TFLOPS on its vector lanes by the figures reported from AMD's disclosures, which would have been unthinkable in an AMD data-centre chip five years ago. The supercomputer customers get their own variant. The MI430X keeps the same package and memory, 432 GB of HBM4, and swaps in compute dies built for 64-bit work, which AMD promises at 288 TFLOPS of hardware FP64, nearly four times the MI355X. It is due in 2027, and it has already been chosen for three national machines: Discovery at Oak Ridge, to be delivered in 2028 as Frontier's successor; Alice Recoque in France, Europe's second exascale system, from 2026; and Herder in Stuttgart in 2027. A third variant, the MI440X, was shown at CES as an eight-GPU server for companies that want MI400 chips without a whole rack, and has no published specifications yet.

Helios

Helios is AMD's first rack designed as one machine, the counterpart of the NVL72 racks of Part 27 and Part 29. It holds 72 MI455X and 18 EPYC processors of AMD's new Venice generation, in eighteen compute trays of four GPUs and one CPU each, with up to three 800 Gb/s network cards per GPU for the connection to the rest of the data centre. Between the compute trays sit six switch trays holding twelve switch chips in all, which join every GPU in the rack to every other. The rack itself is a double-width design called Open Rack Wide, contributed by Meta to the Open Compute Project, and it is liquid-cooled throughout, with the coolant connecting at the back of each tray. AMD's figures for the whole rack are 2.9 exaflops of dense FP4, 1.4 of FP8, 31 TB of HBM4 at 1.7 PB/s, 260 TB/s of bandwidth between the GPUs and 43 TB/s out to the network. Lisa Su told the CES audience it weighs nearly 7,000 pounds, about three tonnes. AMD has not published its power. Schneider Electric's reference design for housing it allows up to 246 kW per rack.

UALink, carried over Ethernet

The switch layer is where Helios departs most from Nvidia. Nvidia's NVL72 racks join their GPUs with NVLink, a protocol Nvidia owns, through switch chips Nvidia makes, over a copper spine Nvidia designed. AMD wanted the same thing built from open standards, and in 2024 it co-founded the UALink consortium with Broadcom, Cisco, Google, HPE, Intel, Meta and Microsoft to write one: a protocol for GPUs to read and write each other's memory directly, the job NVLink does, over lanes of 200 Gb/s, for pods of up to 1,024 accelerators. Version 1.0 was published in April 2025 and version 2.0 in April 2026.

What did not exist in time was a UALink switch chip. Designing a large switch takes years, and as of mid-2026 none was shipping. So Helios carries UALink's messages inside ordinary Ethernet frames, through Ethernet switch chips that already existed, an arrangement AMD and its partners call UALink over Ethernet; in HPE's version of the rack the switches are Broadcom's Tomahawk 6. Each MI455X has 72 lanes of 200 Gb/s into that switch layer, 3.6 TB/s counting both directions, the same headline as a Rubin GPU's NVLink 6. AMD's own measurements at Hot Chips put the usable figure at 3.2 TB/s. Whether a tunnelled open protocol can match a purpose-built proprietary one on latency, when thousands of small messages fly between GPUs at once, is exactly the kind of thing the first customers will find out. It is the Part 15 question, how far a group of GPUs can behave as one, answered with a different kind of plumbing.

Helios against Vera Rubin

Here are AMD's figures beside Nvidia's, with the caveats both companies attach to them.

On paper Helios has the advantage in memory capacity, by half again, and a smaller one in four-bit arithmetic, which is what AMD claimed at the launch: 15 per cent more FP4, 50 per cent more memory, slightly more bandwidth, and, on AMD's own estimate for one large open model at projected prices, up to 30 per cent more tokens per dollar. Two notes on the Nvidia column. Nvidia's 50 PFLOPS FP4 figure, the one usually quoted, is for sparse arithmetic, so the dense training figure is the fair comparison. And Nvidia's specification page, as I read it this month, lists lower memory and NVLink bandwidth than the figures in Part 29, 19.2 rather than 22 TB/s and 3 rather than 3.6 TB/s, without an explanation I can find. The memory-supply problem Part 29 described may be the reason. Neither company's numbers have yet been measured by anyone else.

The contracts came first

The most unusual thing about this generation is that its largest customers signed before it existed. In October 2025 OpenAI agreed to deploy six gigawatts of AMD GPUs over several years, starting with a first gigawatt of the MI450 family in the second half of 2026, and AMD gave OpenAI warrants for up to 160 million AMD shares that vest in tranches as the gigawatts are deployed and as AMD's share price reaches set levels. AMD's finance chief said the deal would bring in tens of billions of dollars. Oracle ordered 50,000 MI450 GPUs the same month, starting in the third quarter of 2026. Meta signed a deal of the same size and structure as OpenAI's in February 2026, six gigawatts with the same warrants, beginning with a custom MI450-based GPU. In July, Microsoft said it would run Helios at scale on Azure, and Anthropic agreed to deploy up to two gigawatts of MI455X in Helios racks from the first half of 2027, alongside an AMD commitment to invest up to $5 billion in Anthropic at some future point. Smaller clouds, the Saudi company HUMAIN, and Cerebras, which plans to pair its own wafer-sized chips with Helios racks, filled out the list.

Notice the unit. These contracts are priced in gigawatts, the electricity a data centre can draw, rather than in chips, because power, not silicon, is now the scarcest input, a theme Part 31 takes up. A rough conversion: if a Helios rack draws up to about 246 kW, a gigawatt of them, before the building's cooling and other overheads, is about four thousand racks, close to three hundred thousand GPUs. Allow for the overheads and a gigawatt contract is of the order of a quarter of a million MI455X-class GPUs. Six gigawatts, spread over several generations, is more than a million.

What has been announced beyond it

AMD has committed to a new Instinct generation every year. The MI500, due in 2027, is described as CDNA 6 on a 2 nm process with HBM4E, in a Helios 500 rack with EPYC processors code-named Verano. The MI600 follows in 2028 in a Helios 600 rack. AMD's claims for these have been rack-against-server comparisons with the MI300X, a thousand times the AI performance in January 2026 and more than two thousand times by July, which compare a whole future rack with an eight-GPU server from 2023 and are best read as statements of ambition rather than measurements.

Where this leaves us

The MI400 generation is AMD catching up on the two things Part 25 said the MI300 lacked. Helios is a rack built as one machine, 72 GPUs in one scale-up domain, which AMD has never sold before, joined through an open protocol rather than a proprietary one and, for now, through Ethernet switches standing in for UALink switches that do not yet exist. And the compute die has finally been unified with the graphics one, so that the same work-group processor, the same wave32 and the same software serve a Radeon and an Instinct. On paper it matches or exceeds Vera Rubin in most rows and leads in memory, the advantage AMD has held at every generation since the MI300X. Whether it does so in a customer's data centre, and in what volume, is the question the rest of 2026 will answer.

That is the last real chip in the series. Two things remain before it is all put back together. The first is the question all of these chips have raised and none has answered: where the watts go, from a single gate to a rack of three tonnes to a contract measured in gigawatts. The second is the chip in your pocket, which is not a GPU at all.

Next: Power: where the 450 watts on a graphics card actually go, why moving a number costs more energy than multiplying it, and the ladder from a 700 W chip to a 120 kW rack to a gigawatt campus.