Venice and Zen 6

Each compute tray in the Helios rack of Part 30 holds four GPUs and one processor. Part 30 gave that processor a single clause. Eighteen trays with one 256-core chip each makes 4,608 processor cores in a rack that everyone describes by its 72 GPUs, and something has to be said about what they are doing there.

I am writing this on 12 November 2026. Two days ago AMD announced general availability of its sixth-generation EPYC processors, the EPYC 9006 family code-named Venice, which it had first shown beside the MI400 in July. Venice is the first product built on AMD's new Zen 6 core. This series is about GPUs, but Part 29 stopped to look at Nvidia's Vera, and I stop here for the same reason. In a rack like this the CPU is designed around the GPUs it feeds. As with the last two parts, almost every performance figure here is the manufacturer's own.

A core made deeper, not wider

Zen 6 is the machinery of Part 5 and Part 8. Part 8 described a CPU core as a fetch-decode-execute loop wrapped in an enormous apparatus for making one instruction stream never wait: deep pipelines, out-of-order execution, branch predictors and large caches. A new core generation is mostly a rebuild of that apparatus.

I expected the headline to be a wider core, one that handles more instructions per tick. It is not. By the figures reported from AMD's launch briefing, Zen 6 still sends eight instructions per tick into its out-of-order machinery and still has six arithmetic units for whole numbers, the same as Zen 5. What grew is everything that lets the core look further ahead. The reorder buffer holds 640 instructions where Zen 5 held 448, and the queues of loads and stores waiting on memory grew with it.

Part 7 explained why that number matters. The reorder buffer is how far a core can keep working past a number that is still on its way from memory. A longer one means more useful work done during each wait, and more trips to memory in flight at once. It is one more way of hiding the memory wall.

The other change is aimed at AI. The core's vector unit, the sixteen-lane AVX-512 arithmetic from Part 6, gained full 16-bit floating-point arithmetic and went from two paths to four for eight-bit dot products. Those are the small number formats that inference runs on. A CPU will not catch a GPU at matrix arithmetic, for all the reasons in Part 8, but a good deal of the work around a model is small enough that sending it to a GPU costs more than doing it in place.

AMD sums up the gain as instructions per clock (IPC), meaning how much work a core gets through in one tick. It is the improvement left over once you set clock speed aside. In July AMD said about 20 per cent over Zen 5. The launch material, as reported by Wccftech, gives an average of 27 per cent, made up of about 20 per cent on business and cloud software and about 31 per cent on AI workloads, measured with both chips held at the same frequency. Those are AMD's measurements on AMD's choice of tests.

Two cores from one design

Zen 6 comes in two layouts, as the last two generations did. They run the same instructions and have the same internal design. The standard core is laid out for clock speed. The compact one, Zen 6c, is laid out to fit as many as possible on a piece of silicon.

This is Part 8's trade between latency and throughput, made inside one company's CPU line. A database that charges by the transaction wants each core to answer quickly and takes the 5.3 GHz part. A cloud provider renting out cores by the hour wants as many as the socket will hold and takes the 256. Both get 4 MB of L3 cache per core.

The largest model, the EPYC 9996, has 256 Zen 6c cores running two threads each, the hyper-threading of Part 7, for 512 threads. It has 1,024 MB of L3 cache, a 600 W power rating and a list price of $14,904. The Zen 5 generation topped out at 192 cores.

The package

The desktop processor photographed in Part 8 had two chiplets of eight cores and a third chip for memory and input-output. Venice is the same plan grown up. AMD showed the bare package at CES in January, and ServeTheHome described what was visible: two large I/O dies in the centre, with eight core chiplets directly flanking them. AMD calls each core chiplet a core complex die (CCD).

The chiplets are made on TSMC's N2 process, the same 2 nm class as the compute dies in the MI455X. The I/O dies are reported to be on 3 nm, and they carry the parts that gain little from the newest process: the memory controllers, the PCI Express links, and the connections between chiplets. Instead of routing those connections through the package underneath, Venice joins neighbouring dies with small silicon bridges, a relative of the bridge-built interposer under the MI455X.

Two things about this layout are worth noticing. The first is the count. A Zen 5 EPYC used up to sixteen core chiplets, and Venice uses eight much larger ones. Part 19 showed that yield punishes area, so choosing bigger dies on a brand new process is a statement of confidence in that process. The second is how familiar it looks. Compute dies on the newest node, I/O dies on an older one, bridges in between. It is the MI455X of Part 30 without the memory stacks, and the same engineers' habits are visible in both.

Memory, again

Every number Part 29 quoted for Vera was about feeding the GPU, and the same is true here. Venice has sixteen memory channels per socket, up from twelve. The arithmetic from Part 6 applies directly. DDR5-8000 moves 8,000 million transfers a second across 64 wires, which is 64 GB/s per channel and about 1 TB/s across sixteen. With MRDIMMs, memory sticks that interleave two sets of chips to double the rate, the figure is 12,800 and the total is 1.6 TB/s, with up to 8 TB of memory per socket. Vera has 1.5 TB at 1.2 TB/s.

Venice also moves to PCI Express 6.0, which carries twice as much per lane as the version before it, for its links to GPUs, network cards and storage.

So the two companies made different choices for the same job. Nvidia put 88 custom cores and soldered laptop-style memory in each of 36 CPUs per rack. AMD put far more cores and far more memory in each of 18, using the standard sticks every server already takes. That is the same split as the rest of the rack, where Nvidia designs each piece for the others and AMD assembles from open parts.

Why a GPU company cares about CPU cores

AMD's argument at the launch was that AI agents have changed what the CPU is for. A chatbot answer is almost all GPU work. An agent that runs code, calls tools and browses does much of that on CPU cores, in an isolated sandbox for each agent, and the GPU waits while it does.

So AMD announced CPU-only racks called Helion, designed to stand beside Helios, holding up to 73,728 threads in one rack. That is the reason for a 256-core part. It is also a claim about where the bottleneck is moving, and the next year will test it.

The usual caution applies. AMD says a two-socket EPYC 9996 server is up to 3.7 times as fast as a Vera system on a standard integer benchmark, but the Vera score in that comparison is AMD's own estimate. ServeTheHome published a first review on launch day. I have used it for specifications and not for performance, so every performance figure in this part is still AMD's.

What has shipped and what has not

What went on sale this week is one platform, built around a large socket called SP7. A smaller socket, SP8, is due early in 2027. Venice-X, with extra cache stacked on the chiplets, is a 2027 product. So is Verano, the version built around low-power LPDDR5X memory that the Helios 500 rack of Part 30 will use. The desktop Ryzen chips that will carry Zen 6 into ordinary PCs have not launched. Neither has Medusa Halo, the laptop chip expected to put the same 12-core chiplet beside a large Radeon GPU, which Part 33 comes back to.

Where this leaves us

I came to Zen 6 expecting a faster CPU and found a CPU reshaped by the GPUs beside it. The core did not get wider. It got better at waiting for memory, which is the problem Part 7 said every processor has. The socket got sixteen memory channels and faster links, because its first job in a Helios tray is to keep four GPUs supplied. And the core count went to 256 because AMD is betting that agents will want a great many ordinary cores close to the GPUs that do their thinking.

Part 8 set the CPU and the GPU against each other as two ways to be fast. In the rack they have stopped being rivals. Each is built on the assumption that the other is there.

That is the last real chip in the series. Two things remain before it is all put back together. The first is the question all of these chips have raised and none has answered: where the watts go, from a single gate to a rack of three tonnes to a contract measured in gigawatts. The second is the chip in your pocket, which is not a GPU at all.

Next: Power: where the 450 watts on a graphics card actually go, why moving a number costs more energy than multiplying it, and the ladder from a 700 W chip to a 120 kW rack to a gigawatt campus.