Part 24 described the H100 and Part 25 AMD's answer to it. Intel had two answers in the same years, built by two different teams, and neither became a lasting business. They are worth a part of their own all the same, because each tried an idea the other companies did not. The first, Ponte Vecchio, took chiplets further than anyone had, and built one of the world's three exascale supercomputers. The second, Gaudi, was an AI accelerator with no GPU heritage at all. And Intel's 2026 card, Crescent Island, makes a bet about memory that neither Nvidia nor AMD has made in a data-centre chip.

A rendering of the Aurora supercomputer in a bright, empty machine room: a long row of black cabinets whose front panels form a blue banner with the word Aurora in large letters and the logos of Argonne National Laboratory, the US Department of Energy, Intel and Hewlett Packard Enterprise
Aurora at Argonne National Laboratory, as Argonne drew it in 2021, two years before the machine was finished. This is a rendering rather than a photograph; the real machine has 166 cabinets holding 63,744 of Intel's Ponte Vecchio GPUs. Image by Argonne National Laboratory, via Wikimedia Commons, public domain.

Ponte Vecchio: forty-seven pieces

Intel's data-centre GPU was sold from January 2023 as the Data Center GPU Max, but it is better known by its code name, Ponte Vecchio, after the bridge in Florence with shops built along it. The name fits. Where the MI300X of Part 25 is twelve logic dies, Ponte Vecchio is forty-seven tiles made on five different processes by two different companies, and it was the most complicated package anyone had shipped when it appeared.

The arithmetic lives in sixteen compute tiles, made by TSMC at 5 nm, each holding eight Xe-cores of the data-centre kind described in Part 11: eight vector engines of sixteen lanes, eight matrix engines twice the width of Battlemage's, and 512 KB of L1 and shared local memory each. The compute tiles sit on top of two large base tiles, made in Intel's own factories on the Intel 7 process, which hold most of the chip's 408 MB of L2 cache, the network that joins the tiles, and the controllers for the memory. Beside the compute tiles on each base tile sit four Rambo tiles, more L2 cache, also Intel 7. Eight stacks of HBM2e, 128 GB in all, sit beside the base tiles, and two Xe Link tiles made by TSMC at 7 nm carry the connections to other GPUs. Eleven small bridges of silicon embedded in the package, which Intel calls EMIB, join the base tiles to the memory, the link tiles and each other.

Ponte Vecchio's forty-seven tiles, drawn from Intel's Hot Chips 2022 presentation and its Max Series disclosures: sixteen compute tiles and eight Rambo cache tiles stacked on two base tiles, eight HBM2e stacks, two Xe Link tiles, and eleven EMIB bridges joining them. The two halves, called stacks, are mirror images. Schematic: positions follow Intel's drawing, sizes do not.

Ponte Vecchio stacks its compute tiles on its base tiles using Intel's Foveros technique, with connections 36 micrometres apart, which is the same idea as the hybrid bonding of the MI300X in Part 19 at four times the spacing. Altogether it holds more than 100 billion transistors, 128 Xe-cores and 128 GB of memory at 3.3 TB/s, and draws 600 W. Its strength was supercomputer arithmetic: 52 TFLOPS of 64-bit floating point, against 34 for the H100's ordinary lanes, and about 840 TFLOPS of 16-bit matrix arithmetic, below the H100's 989 and with no FP8 at all.

Why so many pieces on so many processes? Partly the reasons Part 19 gives for chiplets in general: small tiles yield better, and each piece can be made on the process that suits it. And partly circumstance. Ponte Vecchio was designed while Intel's own factories were struggling, and in July 2020 Intel announced that its next process would be a year or more late, after which the compute tiles were moved to TSMC. The design that resulted worked, but it was hard to build and expensive, and its successors never shipped. Rialto Bridge, a refreshed version, was cancelled in March 2023, and Falcon Shores, meant to merge Intel's GPU and Gaudi lines, was cut back to an internal test chip in January 2025.

Aurora

What Ponte Vecchio did build was Aurora, at Argonne National Laboratory outside Chicago, and its history is the history of Intel's data-centre ambitions in one machine. Aurora was first announced in 2015 as a 180-petaflop system for 2018 built on Xeon Phi, the descendant of Larrabee described in Part 18. When Intel ended that line it was replanned, and in March 2019 it was announced again as the first exascale computer in the United States, for 2021, built on Intel's future Xe GPU. The GPU's delays delayed the machine. Frontier at Oak Ridge, built on AMD's MI250X, became the first exascale computer in May 2022, and Aurora's installation was completed in June 2023.

Each of Aurora's 10,624 nodes holds two Xeon Max processors, Intel's server CPUs with 64 GB of HBM of their own in the package, and six Ponte Vecchio GPUs, which are wired to each other with Xe Link, every GPU to every other, much as the MI300X board of Part 15 wires its eight. In May 2024, using 87 per cent of its nodes, Aurora ran the standard benchmark at 1.012 exaflops, the second machine in the world past an exaflop, and it ran the mixed-precision version that better reflects AI work at 10.6 exaflops.

One of Aurora's 10,624 nodes: two Xeon Max CPUs, each with 64 GB of HBM in its package, and six Ponte Vecchio GPUs joined to each other directly by Xe Link, fifteen pairs in all, with no switch. Each GPU also connects to a CPU over PCI Express, and each node has eight connections to the machine's network. After Argonne's descriptions of the node; layout schematic.

It also showed the cost of Intel's design in the unit Part 31 argues matters most. Aurora draws 38.7 megawatts for its exaflop. Frontier, with an older AMD GPU, reaches a third more on 24.6 megawatts, and El Capitan, with AMD's MI300A, nearly twice as much on 29.7. Per watt, Aurora does well under half the work of either.

The five machines past an exaflop on the June 2026 supercomputer list, by billions of 64-bit operations per joule on the standard benchmark, computed from the list's measured speeds and power. The same order of speed, at very different power bills.

On the June 2026 list Aurora stood fourth, behind the new Chinese machine LineShine, El Capitan and Frontier, and only just ahead of Europe's first exascale system, JUPITER, which reached the same exaflop on two-fifths of the power with Nvidia's Grace Hopper superchips.

Gaudi: an accelerator that was not a GPU

Intel's other data-centre line came from outside. In December 2019 it bought Habana Labs, an Israeli start-up, for about $2 billion, and with it the Gaudi accelerators. Gaudi is not a GPU in the sense of this series. It has no graphics heritage and no SIMT lanes running thousands of threads. Its arithmetic is done by a few large matrix multiplication engines, which are systolic arrays like the XMX engines and tensor cores at a much larger scale, beside a set of smaller programmable tensor processor cores for everything that is not a matrix multiply, each a wide vector processor that runs instructions bundled together by the compiler, the VLIW approach Part 10's side note described in ATI's old chips.

Gaudi's most distinctive feature was its networking. Where an Nvidia server needs NVLink and NVSwitch chips to join its GPUs, and a separate network card per GPU to reach the rest of the data centre, every Gaudi chip had standard Ethernet ports built into the chip itself and used them for both jobs. Gaudi 3, announced in April 2024, has two dies made by TSMC at 5 nm, eight matrix engines and 64 tensor processor cores, 96 MB of on-chip SRAM, 128 GB of HBM2e at 3.7 TB/s, and twenty-four 200-gigabit Ethernet ports, and is rated at 1,835 TFLOPS of dense BF16 or FP8 arithmetic within 900 W. That is close to the H100's FP8 figure and nearly twice its BF16.

Gaudi 3, after Intel's white paper: two dies, each with four matrix multiplication engines, thirty-two tensor processor cores, 48 MB of SRAM, four stacks of HBM2e and twelve 200 Gb/s Ethernet ports on the die itself. There is no GPU-style array of lanes, and the networking that other chips leave to separate switches and cards is built in. Schematic.

On paper it was competitive, and on price Intel undercut Nvidia heavily. It did not sell. In October 2024 Intel said it would not reach its target of $500 million of Gaudi sales that year, and its executives blamed software: Gaudi was programmed through Habana's own compiler and libraries, which ran the common models in PyTorch well but anything unusual poorly, and offered nothing like the CUDA of Part 14 for writing kernels of one's own. Few large customers beyond IBM's cloud adopted it. When Intel cancelled Falcon Shores in January 2025, its co-chief executive said the company had learned that it was not enough to just deliver the silicon, and that its next design would be a whole system at the scale of a rack, code-named Jaguar Shores.

Crescent Island

Intel's data-centre GPU for 2026 is a different kind of product again. Crescent Island, announced in October 2025 and described in detail at the Hot Chips conference in August 2026, is a single air-cooled PCI Express card of 350 W built for one job, running trained models, not training them. Its GPU uses the Xe3P architecture, the same generation as the next Intel laptop graphics: 32 Xe-cores with 256 matrix engines about four times the size of Battlemage's, now with FP8 and four-bit formats, 32 MB of L2 cache, 512 KB of L1 per core and a 1 MB register file per core, twice Battlemage's.

The bet is in the memory. Crescent Island has no HBM. It carries 160 GB of LPDDR5X, the memory used in laptops and phones, and Intel says board makers can fit up to 480 GB. LPDDR5X is far cheaper per gigabyte than HBM, uses less power, needs no interposer, and, in 2026, is actually available, at a time when HBM is sold out years ahead. What it gives up is bandwidth. Intel has not published Crescent Island's, and estimates by outside observers range from well under 1 TB/s to about 1.3 TB/s, against 8 TB/s for an MI355X or a B200.

Part 12's roofline says exactly what that trade means. Generating text one token at a time is limited by bandwidth, so a single conversation on Crescent Island will be slow, several times slower per token than on an HBM GPU. But capacity sets how many conversations, and how long a context, a card can hold at once, and serving many of them together, batched as Part 12 described, raises the arithmetic done per byte read. Intel's pitch is a card for what it calls agentic AI, long-running assistants with very long contexts, where the cost of holding the context in memory dominates and a few more milliseconds per token do not. It is the same trade as the Strix Halo laptop of Part 22 and Nvidia's DGX Spark, a lot of slow memory, made at data-centre scale. As I write, Intel expects to sample Crescent Island to customers in the second half of 2026, and its full launch may slip into 2027. No independent measurements exist yet.

By the numbers

Data Center GPU Max 1550 Gaudi 3 Crescent Island H100 SXM MI300X
Launched January 2023 2024 sampling 2026 2022 2023
Silicon 47 tiles on 5 processes 2 dies, 5 nm Xe3P GPU 1 die, 4 nm 12 dies, 5 and 6 nm
Transistors more than 100 billion not published not published 80 billion 153 billion
Memory 128 GB HBM2e 128 GB HBM2e 160 GB LPDDR5X 80 GB HBM3 192 GB HBM3
Bandwidth 3.3 TB/s 3.7 TB/s not published 3.35 TB/s 5.3 TB/s
FP16 or BF16 matrix, dense about 840 TFLOPS 1,835 TFLOPS not published 989 TFLOPS 1,307 TFLOPS
FP8, dense none 1,835 TFLOPS supported 1,979 TFLOPS 2,615 TFLOPS
FP64 52 TFLOPS not a target supported 34 vector, 67 matrix 82 vector, 163 matrix
Links 16 Xe Links 24 × 200 Gb Ethernet PCIe 5.0 NVLink, 900 GB/s 7 × 128 GB/s
Power 600 W 900 W 350 W 700 W 750 W

Where this leaves us

Intel's data-centre accelerators tried three distinct ideas. Ponte Vecchio took chiplets furthest, forty-seven tiles on five processes, and built an exascale supercomputer, at a power cost that its competitors' machines did not pay. Gaudi tried to win with large matrix engines, built-in Ethernet and a low price, and lost on software. Crescent Island bets that for the next wave of AI, long-running agents serving long contexts, memory capacity at low cost matters more than memory speed. Of the three, only the first has been measured at scale and only the last is still a live plan, with Jaguar Shores, a rack-scale design using HBM, promised after it.

The common thread is the one this series keeps finding. Intel's silicon was often interesting and sometimes competitive on paper; the software, the systems and the persistence that turn silicon into a platform are what it lacked. The next part is Nvidia's own next step, which is more about systems than about silicon.

Next: Blackwell: two dies on one package, 208 billion transistors, FP4, the 72-GPU rack, and the RTX 50 series that brought the same generation to gamers.