Vera Rubin

I am writing this at the end of August 2026, which is an awkward moment to write about Vera Rubin. Nvidia detailed the architecture at its GTC conference in March 2025, said the chips had taped out that August, announced them "in full production" at CES in January 2026, added more detail at GTC in March 2026, and has promised them to customers in the second half of this year. Cloud providers have announced racks for the same window. What I cannot find, as of today, is an independent benchmark of a Rubin GPU, because as far as public reporting goes, they are not yet in customers' hands in volume. So this part is written from announcements, and I will be explicit about which numbers are stated targets rather than measured facts. If you are reading this in 2027, some of them will have moved.

The name is the astronomer Vera Rubin, whose measurements of galaxy rotation gave us the evidence for dark matter, and Nvidia split it in two: Vera is the CPU and Rubin is the GPU. That the CPU gets equal billing is itself the story. This is the first generation designed from the outset as a rack, where the processor beside the GPU is Nvidia's own, built for the job of feeding it.

The GPU

Rubin keeps Blackwell's shape and changes everything inside it. Two reticle-sized compute dies per package, now on a 3 nm-class TSMC process, the first real shrink since Hopper and Ada moved to 4N in 2022, with the memory and interconnect controllers split out onto separate dies alongside them. Nvidia's architecture post puts the package at 336 billion transistors, 224 SMs, and 896 tensor cores, against Blackwell's 208 billion. The shrink bought about sixty per cent more switches in the same two reticles.

The memory is the headline. Each Rubin package carries 288 GB of HBM4 across eight stacks, and HBM4 doubles the width of each stack's interface from 1,024 to 2,048 wires. That is the whole HBM philosophy from Part 8, bandwidth through width rather than speed, applied once more. Nvidia's stated target is 22 TB/s per GPU, nearly three times Blackwell's 8 TB/s. Here is the first place where I have to hedge. Reporting through late 2025 said the memory suppliers were struggling to hit the pin speeds that 22 TB/s requires, and that early units might land nearer 20 TB/s. Nvidia repeated the 22 TB/s figure at CES in January 2026. So take 22 as the target and expect the first shipping parts to be somewhere close to it. Either way, the memory-bound work of Part 8, which is to say a chatbot typing its answer, speeds up by well over double on the same model with not one change to the arithmetic.

The arithmetic changed too. Nvidia's specification page quotes 50 PFLOPS of NVFP4 inference per GPU against Blackwell Ultra's 15, 35 PFLOPS of NVFP4 for training, which runs slower because it accumulates in higher precision, and 17.5 PFLOPS of FP8. Only the FP8 row is explicitly marked as a dense figure, so read the others with the asterisk from Part 9 in mind. The page also marks every figure as preliminary and subject to change, and there is no whitepaper yet. The direction is not in doubt. Between the shrink, the wider tensor cores, and the third pull on the FP4 lever, the sixth-generation tensor core does several times the matrix work per package.

NVLink moves to its sixth generation at 3.6 TB/s per GPU, double Blackwell's, by doubling the signalling rate on each wire of the copper backplane. And the rack keeps the same shape: 72 Rubin packages and 36 Vera CPUs in the same Oberon rack design that holds GB200 and GB300, with 260 TB/s of NVLink bandwidth across the domain, 20.7 TB of HBM4 delivering 1,580 TB/s in aggregate, 54 TB of CPU memory, and, by Nvidia's dense figures, 3.6 exaFLOPS of NVFP4 inference and 1.26 exaFLOPS of FP8 training in one rack. Nvidia calls it the Vera Rubin NVL72.

A note on counting to 144

You will see the same rack called the NVL144 in material from 2025, and it is worth knowing why, because it is a small window into what "a GPU" now means. At GTC 2025 Nvidia announced that it would start counting compute dies rather than packages, on the grounds that each Rubin package holds two of them, and named the rack NVL144 accordingly. That proved confusing for everyone, since the same rack held 72 sockets exactly as its Blackwell predecessor did, and by the CES keynote in January 2026 Nvidia had quietly reverted to counting packages. The rack was launched as NVL72. Some Nvidia pages and a good deal of press still say 144. They are the same machine. The episode is a reminder that the question Part 15 raised, of whether the die, the package, or the rack is the unit, now has no settled answer even inside Nvidia.

The CPU

Grace, the CPU in the GB200 racks, used off-the-shelf Arm Neoverse cores. Vera uses 88 cores of Nvidia's own design, code-named Olympus, each running two threads for 176 in all, with up to 1.5 TB of LPDDR5X memory at 1.2 TB/s, and an NVLink-C2C link to the GPU at 1.8 TB/s, double Grace's. Every one of those numbers is about the GPU. The CPU's job in this rack is to move data, run the parts of inference that are a chain rather than a matrix, and act as a very large, moderately fast overflow for the GPU's memory, exactly the coherent-spill arrangement of Part 11. A conversation's growing cache of past tokens, which can run to gigabytes for long chats, lives partly in Vera's 1.5 TB and is pulled across the 1.8 TB/s link as needed. That is why the link bandwidth got doubled and why the CPU is co-designed rather than bought.

The GPU that only reads prompts

The most interesting chip in the generation was announced separately, in September 2025, and it is a direct consequence of the roofline from Part 8. Serving a language model has two phases with opposite shapes. Prefill, reading the prompt, touches every weight once for every token in the prompt at the same time, so it is compute-bound, and a long prompt or a large document makes it more so. Decode, generating the answer, touches every weight once per output token, so it is memory-bound, and no amount of arithmetic helps. An HBM-equipped Rubin is the right machine for decode and a wasteful one for prefill, where its scarce, expensive memory bandwidth sits idle while the tensor cores work.

Rubin CPX is a GPU built for prefill alone. It has 128 GB of GDDR7, the gaming memory from Part 15, rather than HBM, because prefill does not need the bandwidth and GDDR7 is a fraction of the cost. It has 30 PFLOPS of NVFP4 and a hardware attention unit tuned for very long contexts. It is meant to sit in the same rack as ordinary Rubin GPUs, take the prompt, compute the model's internal state for it, and hand that state across NVLink to a Rubin GPU that does the generating. Nvidia calls the arrangement disaggregated inference and the combined rack the Vera Rubin NVL144 CPX, and that name has kept the 144 for now. CPX is due at the end of 2026, so it is one step further from my desk than Rubin itself.

I find this the most satisfying design in the series, because it is Part 8 made into silicon. For a decade the answer to every workload was "the GPU". Now the workload has been split along the ridge of the roofline, and each half gets a chip with the memory it actually needs.

What has been announced beyond it

Nvidia now publishes a roadmap a couple of years out, and two more generations were on the slide at GTC 2026. All of this is announcement, not product.

Nvidia does not publish rack power figures. The Blackwell numbers come from the server makers' own documentation. The Rubin figures are supply-chain estimates for two power profiles of the same hardware, repeated more often than independently confirmed. The Rubin Ultra figure is the one Nvidia used on stage in 2025, and the rack has been redesigned since.

Rubin Ultra, due in the second half of 2027, puts four reticle-sized dies in one package with a terabyte of HBM4e, roughly doubling everything per package again. It needs a new rack, called Kyber, that holds 144 packages, which is where the NVL576 name comes from once you count dies. When Nvidia first showed Kyber in 2025 it estimated around 600 kW per rack, five times the GB200 rack that already needs liquid cooling. The version shown at GTC 2026, with a Rubin Ultra tray on display, is about half as dense, so the final number is unsettled. After that comes an architecture called Feynman, sketched for 2028 with a successor CPU, and about which nothing else useful is known.

I have left out several things Nvidia announced alongside Rubin, the new network chips, the data processing units, a partnership that puts a different kind of inference chip in the same rack, because they belong to a series about datacentres rather than one about GPUs. The 1.6 terabit network card per GPU is worth a mention only because it fills in the bottom rung of Part 11's ladder for this generation: 200 GB/s off the rack against 22 TB/s on the package, still a factor of a hundred.

Where this leaves us

Three trend lines run through the last four parts, and Rubin extends all of them. Dies per package: one, then two, then two, then four. Bits per number in the tensor cores: sixteen, then eight, then four, and the same four again. Rack power: 120 kW in 2024 to something in the hundreds of kilowatts by 2027, whatever the final Kyber number turns out to be. Behind all three is the fact this series has repeated since Part 5: the arithmetic was never the hard part, and each generation is mostly a bigger, wider, closer, cheaper way of moving bytes to it. HBM supply, not transistor count, is now the number that decides how many Rubins get built.

Everything in this part before the table is confirmed by Nvidia's own statements and by named customers. The performance figures are Nvidia's, unmeasured by anyone else as I write. The memory bandwidth is a target with a known wobble. Treat the whole part as a photograph of a machine still being unpacked, and check the numbers against a whitepaper once one exists.

That is the last real chip. What remains is to put the whole series back together, from switch to rack, and to hand you the one skill it was all building toward: reading a GPU spec sheet and knowing what every line means.

Next: The Whole Picture: the full stack from transistor to rack in one diagram, a guide to every line on a spec sheet, the three questions to ask of any chip, and a glossary to keep.