Blackwell

Part 14 ended at a wall. The GH100 die is 814 mm², and the machines that print chips cannot expose an area much larger than about 850 mm² in one shot. Nvidia could not make Hopper's successor by making a bigger chip. Shrinking the transistors would have helped, but the next process node was not ready in the volumes needed, so Blackwell stayed on a 4 nm-class process, TSMC's 4NP, a tuned version of what Hopper used. Same size limit, same transistor density, and the customers wanted several times the performance. What do you do?

You make two, and you join them so well that the software cannot tell. Blackwell, announced in March 2024, is two reticle-sized dies of about 104 billion transistors each, side by side on one package, connected by a seam Nvidia calls NV-HBI (high bandwidth interface) that carries 10 TB/s between them. That is more than the bandwidth of either die's memory, so a lane on the left die reaching a number in the right die's HBM sees roughly the speed it would see reaching its own. There is one L2 across both, one memory space, one GPU as far as CUDA is concerned. The chip has 208 billion transistors, and it got there without a single one of them being smaller than Hopper's.

By the numbers

The pattern from Hopper continues: the lanes barely feature, and the memory does. Eight stacks of HBM3e give 8 TB/s, two and a half times Hopper's bandwidth, and up to 192 GB of capacity. (Nvidia's launch material says 192 GB. The shipping HGX B200 datasheet lists 180 GB and 7.7 TB/s, presumably with some of each stack reserved for yield, and both figures are fair depending on what you are counting.) NVLink doubles to 1.8 TB/s. FP8 throughput more than doubles, which is roughly what two dies buy you. And then there is a new row, FP4, at twice the FP8 rate, which is where the headline claims of several times Hopper's inference performance come from. Power rises by nearly half again, which is the price of two dies on a process that did not get more efficient.

Four bits, with a scale for every sixteen numbers

The fifth-generation tensor core's new format is FP4, two exponent bits and one mantissa bit, and if you tried it in the demo in Part 9 you saw what that means: sixteen possible values, eight magnitudes and a sign, a largest value of 6, and errors of twenty per cent on an unlucky number. On its own it is nearly useless. What makes it work is the second-generation Transformer Engine and a technique Nvidia calls micro-tensor scaling. Instead of one scale factor per tensor, as Hopper used for FP8, Blackwell keeps a scale factor for every small block of numbers, sixteen in the NVFP4 format, thirty-two in the industry-standard MX formats it also supports. Each block is scaled into FP4's tiny range individually, so a tensor with a few large values does not force all the small ones to zero. The scales are stored in eight bits each, a true FP8 value for NVFP4 and a plain power of two for the MX formats, with one further FP32 scale for the whole tensor. Roughly four and a half bits per number all in, at half the size and double the tensor throughput of FP8, and in practice, for the weights of a trained model, with an accuracy loss small enough that most deployments accept it.

This is the last pull, for now, on the lever that has driven every generation since Volta. FP32 to FP16 to FP8 to FP4, and each step halved the bytes per number, which for the memory-bound work of Part 8 is worth as much as the extra arithmetic. A model stored in FP4 moves a quarter of the bytes per token that it did in FP16. Combine that with 8 TB/s of HBM and you get Blackwell's inference numbers, and now you can see that most of them are format and memory, not lanes.

The rack is the product

With Hopper, the unit Nvidia sold was an eight-GPU HGX board. With Blackwell, it is the rack. The GB200 NVL72, introduced in Part 11, holds 36 GB200 superchips, each one Grace CPU and two Blackwell GPUs, across 18 compute trays, with 9 trays of NVLink Switch chips wiring all 72 GPUs into one 130 TB/s domain. The rack has 13.4 TB of HBM3e and 17 TB of LPDDR5X, weighs over a tonne, draws around 120 kW, and is liquid-cooled throughout, since the GPUs run at up to 1,200 W each and there is no moving that much heat with fans. The whole thing is delivered assembled and turns on as one machine. NVLink 5 can extend the domain to 576 GPUs with more switches, but 72 became the standard size. CoreWeave brought the first GB200 NVL72 racks into general availability in February 2025, and by the end of that year the largest AI installations in the world were made of them.

A year after the B200, Nvidia shipped Blackwell Ultra, the B300 and its GB300 NVL72 rack. Same architecture, same two dies, but 288 GB of HBM3e per GPU using taller twelve-high stacks, dense FP4 throughput raised by half, from 10 to 15 PFLOPS per GPU in the rack versions, the special function units doubled to speed up the attention calculation, and power up to 1,400 W. It is the pattern from the H100 to the H200 again, more memory on the same silicon. CoreWeave deployed the first GB300 NVL72 racks in July 2025 and had them in its cloud by August.

The parts nobody puts in the keynote

Blackwell also picked up a set of features that only make sense once a GPU is a rack in a datacentre. A decompression engine unpacks compressed database formats at hundreds of gigabytes a second, so that the data-processing jobs that feed model training can run on the GPU without the CPU decompressing first. A RAS engine (reliability, availability, serviceability) monitors thousands of internal signals to predict failures before they take down a training run, which matters when a run spans tens of thousands of GPUs for months and a single failure costs hours. Confidential computing extends to the NVLink fabric, so that a model can run encrypted across a whole rack. None of these is arithmetic. All of them are what it takes to operate a machine the size of a room.

The gaming Blackwell

The same generation reached gamers in January 2025 as the GeForce RTX 50 series, and the top chip, GB202, shows how the two halves of the family differ. It is a single die, 92.2 billion transistors, about 750 mm², on plain TSMC 4N rather than 4NP. The RTX 5090 uses 170 of its 192 SMs, so 21,760 lanes, and swaps HBM for 32 GB of GDDR7 on a 512-bit bus at 1.79 TB/s, the new memory using three-level signalling to push more bits per wire, exactly the wire-limited route Part 8 described. It draws 575 W. The tensor cores are the fifth generation with FP4, and the RT cores the fourth.

The interesting part is what it does with the tensor cores. DLSS 4 replaces the convolutional network that had upscaled frames since Turing with a transformer, the architecture of LLM Basics, running in real time on every frame. And it extends Ada's frame generation to produce up to three invented frames for every rendered one, so that three quarters of what reaches the screen came from the tensor cores. A January 2026 update, DLSS 4.5, pushed that to five of every six frames with a second-generation transformer. Blackwell also lets a game's own shader code call small neural networks directly, which Nvidia calls neural shaders, for things like compressing textures and approximating complex materials. A gaming GPU in 2026 spends a large and growing share of its time evaluating w × x + b rather than drawing triangles, and the line between the graphics chip and the AI chip has become a matter of memory type and NVLink.

For the home model runner, the arithmetic of Part 13 updates itself: 32 GB at 1.79 TB/s means a 30-billion-parameter model at 4 bits fits with room for a long conversation and sweeps its weights nearly a hundred times a second, and FP4 tensor cores mean that a model quantised to NVFP4 gets hardware support rather than being unpacked on the fly.

Where this leaves us

Blackwell answered the reticle wall by redefining the chip as a package, and then redefined the product as a rack. Along the way it took the precision lever to four bits, doubled NVLink, more than doubled memory bandwidth, and nearly doubled power. The unit of "a GPU" is now 72 packages of two dies each, sharing 13 TB of memory across a 130 TB/s fabric, in a box that draws as much as a small street. Every one of those moves was forced by the same three facts this series has repeated since Part 5: compute is cheap, bytes are expensive, and the models will not fit.

Which raises the question of what comes after two dies. The answer, announced in 2025 and reaching customers as I write, is more dies, faster memory, and a rack that keeps its shape while everything inside it doubles.

Next: Vera Rubin: the 2026 generation, HBM4, NVLink 6, a CPU built for the rack, a GPU built just for reading prompts, and what has actually shipped versus what has been announced.