Ada Lovelace is the chip I keep returning to in this series, because it is the one most readers will have met, in a gaming PC or behind a rented cloud instance. It launched in October 2022 as the GeForce RTX 40 series, and its largest die, the AD102, is the 76.3 billion transistors, 608.5 mm² of TSMC 4N silicon that Part 2 opened with. It is a gaming chip. It renders games at a pace that made the previous generation look tired. And when I read its whitepaper, what struck me was that almost every new idea in it is about AI, either directly, in the tensor cores, or indirectly, in how it uses neural networks to draw pictures. This part is what a full Ada looks like with the vocabulary of Parts 7 through 10 in hand.
The die
Here is the AD102 by the numbers from the Ada whitepaper. Twelve GPCs. Each GPC has six TPCs, each TPC two SMs, so 144 SMs in all. Each SM is the four-partition design from Part 7: 128 lanes, four fourth-generation tensor cores, 256 KB of registers, 128 KB of L1 and shared memory, and one third-generation RT core. That gives the full die 18,432 lanes, 576 tensor cores, and 144 RT cores. Down the middle runs the L2 cache, and around the edges sit twelve 32-bit memory controllers, a 384-bit bus to GDDR6X.
The card you can buy, the RTX 4090, does not use the whole die. It has 128 SMs enabled out of 144, giving 16,384 lanes, 512 tensor cores, and 128 RT cores, with 24 GB of GDDR6X at 1,008 GB/s, a boost clock of 2.52 GHz, and a 450 W power budget. The sixteen disabled SMs are the yield story from Part 7: not every one of the 144 comes out of the fab working, and a product that needs only 128 can use far more of the wafers. No shipping product uses all 144. The closest are the L40 and L40S data centre cards, the same silicon sold for inference and rendering servers, with 142 SMs enabled.
The cache that grew sixteen times
The most revealing number on the die is the L2. Ampere's GA102 had 6 MB. AD102 has 96 MB, of which the RTX 4090 gets 72. Nothing else on the chip grew anything like that much, and the reason is Part 8 in one comparison. The RTX 3090's memory delivered 936 GB/s. The 4090's delivers 1,008 GB/s, eight per cent more. But the 4090's lanes do 82.6 TFLOPS against the 3090's 35.6, more than double. Bandwidth per operation halved in one generation, because GDDR on a circuit board had run into the wire limit and HBM was too expensive for a gaming card.
So Ada moved the roofline ridge the only way left: catch more reuse on the die. A 72 MB L2 holds the working set of a game frame, the textures and geometry being read repeatedly, so that most of those reads never go out to GDDR at all. For AI it does the same for the tiles of a matrix multiply that do not fit in shared memory. The whitepaper is candid that this was the single biggest design change in the generation, and it is the same move AMD had made a year earlier with its own large cache. When memory bandwidth stalls, cache is where the transistors go.
Ray tracing, and a fix for divergence
The RT core deserves a proper explanation, because it turns out to be a story about Part 7. Traditional rendering works out what each triangle in the scene looks like from the camera. Ray tracing works the other way: for each pixel, it shoots a ray into the scene, finds what it hits, and bounces onward to find what lights that point. The expensive part is the finding. A scene has millions of triangles, and a ray must not test all of them, so the triangles are organised into a tree of nested boxes, a bounding volume hierarchy, and a ray descends the tree testing boxes until it reaches a handful of triangles to test exactly. The RT core is a unit that does those box and triangle tests in hardware, thousands of times faster than the lanes could, and Ada's third-generation version doubles the triangle test rate of Ampere's and adds two engines for handling very fine geometry and partly transparent surfaces.
Here is the catch. Rays are the worst possible workload for a warp. Thirty-two neighbouring pixels shoot thirty-two rays, they hit thirty-two different surfaces, and each surface wants a different material calculation. That is divergence at its most extreme, and every warp spends most of its time with most of its lanes masked off. Ada's answer is Shader Execution Reordering (SER): after the rays have found their hits, the hardware reshuffles threads across the SM so that threads about to run the same material code are gathered into the same warps. The whitepaper measures up to a 44 per cent speedup in the most heavily ray-traced game of the day. It is a direct, hardware-level fix for the problem the divergence demo in Part 7 showed, and it exists because ray tracing made the problem unavoidable.
Half the frames you see are inferred
Turing's DLSS rendered a frame at low resolution and used a neural network on the tensor cores to upscale it. Ada's DLSS 3 goes further: it uses a neural network to generate entire frames that were never rendered. The GPU renders frame one and frame two, and a network, fed with both frames, with the game's own record of how objects moved, and with a map of pixel motion computed by a new unit called the optical flow accelerator, produces a frame in between. The display shows one, then the invented one, then two. Roughly half the frames on screen came from w × x + b on the tensor cores rather than from the rendering pipeline. When it works, the frame rate roughly doubles on top of whatever upscaling already gave you. When it does not, you see the artefacts that made it controversial. Either way, it was the moment the tensor core stopped being a feature for AI researchers and became the thing that decides how smooth a game feels.
The tensor cores themselves are Ada's fourth generation, and their new trick is the FP8 format from Part 9: 660 TFLOPS dense, or the 1.3 PFLOPS headline with sparsity. That is the same tensor core generation as Hopper, on a gaming card, and it is why a 4090 became the default machine for people running language models at home.
Ada as a home AI machine
Put the numbers together the way Part 8 taught. A 4090 has 24 GB of memory and reads it at 1 TB/s. An 8-billion-parameter model quantised to 4 bits is about 4.5 GB, so it fits easily, and the card can sweep through its weights over 200 times a second, which is an upper bound of around 200 tokens a second. A 30-billion-parameter model at 4 bits is around 18 GB, still inside the 24 GB, and tops out somewhere around 50 tokens a second. A 70-billion-parameter model at 4 bits is 40 GB and does not fit, which is why 70B is where home users start talking about two cards. None of this has anything to do with the 4090's astonishing tensor throughput, which sits mostly idle during generation. It is memory capacity and memory bandwidth, and the 4090 happened to have the best combination that consumer money could buy. The rest of the card, all the ray-tracing hardware, video encoders, and display logic, is dead weight for that job, and that is precisely the difference between this chip and the next one.
Where this leaves us
Ada is the maximal graphics chip: a Maxwell-style SM scaled to 144 copies, a huge cache to make up for stalled memory bandwidth, hardware for ray tracing, and a fix for the divergence that ray tracing causes. Its new AI parts, FP8 tensor cores and neural frame generation, are there to draw better pictures. And yet the same tensor cores, the same 4N process, and nearly the same transistor budget were, in the same year, spent on a chip with no ray tracing, no display outputs, no video encoders, and no game in mind. That chip is Hopper, and putting the two side by side is the clearest picture I know of what "an AI chip" actually means.
Next: Hopper: the H100, 80 billion transistors spent entirely differently from Ada's 76, HBM3, the Transformer Engine, and the features that let SMs cooperate with each other for the first time.